1. Field of the Invention
The present invention relates to a display control circuit which controls transfer of display data from a random access memory (RAM) in which the display data is stored to a display and more particularly, it relates to a display control circuit which prevents conflict between a write/read operation of the display data by a CPU and a transfer operation of the display data from a single port RAM to a display in a display circuit which stores the display data in the single port RAM and displays the data.
2. Description of the Related Art
The single port RAM is incorporated and when the display data is written on/read from the single port RAM by the CPU and the display data is transferred from the single port RAM to a display panel (display), the display data could be destroyed because of conflict between a write/read command and a command of display read. In order to prevent the data from being destroyed because of conflict, various kinds of measures have been taken. For example, Japanese Unexamined Patent Publication No. 63-234316 discloses a method of controlling validation and invalidation of access by providing an access judgment circuit, and a method of determining an object which can be accessed in a predetermined period. In addition, Japanese Unexamined Patent Publication No. 2003-288202 discloses a method of stopping an access from the CPU by providing a flag while display data is read, and an internal synchronization circuit to improve a defect in which a cycle time between a write/read process and a display data read process becomes long.
According to the method disclosed in the Japanese Unexamined Patent Publication No. 63-234316 and the conventional circuit disclosed in the Japanese Unexamined Patent Publication No. 2003-288202, the access from the CPU is stopped while the reading period of the display data to prevent the processes from conflicting. According to this method, as stated in the Japanese Unexamined Patent Publication No. 2003-288202, there are problems in which a control load on the side of the CPU is increased, and a cycle time of the transfer of the display data through the RAM becomes long.
The Japanese Unexamined Patent Publication No. 2003-288202 discloses a circuit in which the access from the CPU has priority by stopping a reading request of the display data.
According to the Japanese Unexamined Patent Publication No. 2003-288202, when the access from the CPU is generated while the reading of the display data is requested, a flag to determine whether the read of the display data is completed or not is needed, so that a delay circuit and the like is needed to form the flag, which complicates the circuit. In addition, when a circuit to determine a period of reading the display data comprises only the delay circuit, since a delay time depends on a difference or variation in manufacturing condition, it is necessary to confirm that there is no problem in a circuit operation in a case where a process condition is changed because, for example, a factory is changed, and it is necessary to change and design again the number of stages of the delay circuit, a transistor size and the like in some cases.